1. Technical Field
This invention relates to a control circuit for an output clock of a clock multiplier used for optical transmission equipment and multiplexers in a digital transmission system. More specifically, the invention relates to a control circuit for a clock multiplier capable of controlling the output signal when a multiplied signal is present at the output due to influences of noise while no input clock signal is applied to the input of the clock multiplier.
2. Background Art
A clock multiplier may be required, for example, in a general digital system, when the speed of a main processing unit is set at V/x to get phase margin regarding the processing in a system, in which processing is implemented by the speed V at the input and by the speed V at the output. To output from the system such a signal processed at the speed V/x as a signal with the speed V, data must be converted into data with the speed V on the basis of a clock having the speed V/x used for processing multiplied x times.
A clock multiplier is required in the situation described above. In a conventional clock multiplier, a limiter amplifier is provided in order for restituting a loss occurring when a signal is fed to the input terminal of the clock multiplier, a loss caused by an insertion of a band pass filter, and the like. To sufficiently restitute such losses, a limiter amplifier having a gain of about 32 dB is typically used. However, when the limiter amplifier has a high gain, input of noise may be amplified even if no input signal is applied. Upon amplification of noise, a signal having amplitude and frequency equivalent to the multiplied clock obtainable when an input signal is applied, can be produced at the output terminal.
Though no known publication properly discloses a control circuit for a clock multiplier that controls the output of a multiplier as last mentioned, Japanese Unexamined Patent Publication Sho No. 56-47,139, does disclose control of an output clock. The control circuit shown in this Japanese Patent Publication includes a circuit for detecting signal loss and a gate circuit are inserted between the output of the regenerated clock signal and an output terminal. With the control circuit thus constituted, particularly when a high frequency signal is used as a clock signal, the gate circuit to be inserted is required to have high performance electrical characteristics, representatively, such as rise time. Such a gate circuit, however, is expensive. The number of connection points for a high frequency signal increases in order to insert the gate circuit, thereby inducing waveforms of the clock signal to be impaired.